1. Field of Disclosure
The present disclosure relates generally to Integrated Circuit testing, and more specifically to a scalable scan-based architecture with reduced test time and power consumed during testing.
2. Related Art
Integrated circuits (IC) generally need to be tested after fabrication. One technique for testing ICs is scan-based testing. Scan-based testing generally refers to a technique in which registers (or more generally storage elements) in the IC are connected serially to form a shift register, often termed a scan chain. A test pattern (test vector) from an external test equipment is then shifted serially into the scan chain.
Once the test vector is loaded in the scan chain, a functional test is performed, with each bit in the test vector being provided as in input to a corresponding combinational logic. The output bit of each combinational logic is captured back in a scan chain, and the captured data is then shifted out to the test equipment. The test equipment then compares the captured data with a desired response.
It is generally desirable to reduce test time, and power consumed. Test time during a scan-based test generally refers to the total length of time needed to load (serially shift in) a test vector into a scan chain, perform a functional test and provide (serially shift out) the results of the test. Test time is inversely proportional to the speed (frequency) at which the test vector and response are shifted through the scan chain.
On the other hand, power consumed in the IC during testing is generally directly proportional to frequency at which the test vector and response are shifted through the scan chain. In general, it is desirable that a scan-based test architecture reduce both the test time as well as the power consumed in an IC during a scan-based test.
It may be desirable that the approach also be scalable. Scalability of a scan-based test architecture generally refers to the ability of the architecture/approach to accommodate a larger number of flip-flops. The approach often needs to be designed while keeping the test time and power consumption within acceptable levels.
Several aspects of the present invention provide a scalable scan-based test architecture with at least one of reduced test time and power.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.